Overview of DOLORES
Presentation of the DOLORES project
Context
Artificial intelligence (AI) and more specifically deep learning (DL) architectures have received increasing attention in recent years, solving problems that have resisted the research community for many years. Yet, the computational demands of DL architectures are doubling every six months, pushing the limits of current hardware. This has given rise to domain-specific hardware accelerators such as Google’s tensor processing unit (TPU), specifically designed for large, complex neural network (NN) models using matrix multiplications. However, we are reaching a stage where microelectronics is encountering physically fundamental bottlenecks in speed, energy consumption, heating, and interconnect delay, which can no longer be resolved by scaling. This situation is even more severe for applications with an additional requirement for speed, such as autonomous driving, Metaverse and computer vision. Breakthroughs are urgently required to meet the rapidly growing demand for computing power and energy efficiency. The age of intelligence calls for the introduction of new devices, new integration technologies, and new architectures for computing.
Neurons in Silicon, powered by light
Light offers unmatched speed, parallelism, and energy efficiency making it an ideal platform for neural network computation. Optical systems naturally perform linear algebra operations, such as matrix multiplications, which are central to AI workloads. With advances in integrated photonics, we can now build compact, scalable, and ultra-fast neural processors that compute at the speed of light. However, optical computing still faces some limitations, especially in terms of numerical precision. Due to noise accumulation in the optical analog computing systems, current optical matrix vector multiplication (MVM) for neural network applications face difficulties to obtain a numerical precision beyond 4-bits (INT4).
The DOLORES project
In order to enhance the numerical precision in optical neural network computations, DOLORES aims to explore and develop a digital optical computing platform. The digital optical computing platform is a radically new concept that incorporates an all-digital architecture that is fundamentally different from any ONN scheme. Integrating the best from photonics and electronics, the digital optical computing platform is expected to revolutionize optical computing, and in the long-term vision enable new possibilities that are barely supported by today’s computing hardware.
Work packages (WPs) for DOLORES
Note that the objectives listed here are simplified without specifications.
WP1: Development of photonic and electronic integrated circuits
Objectives:
- Design and develop of power-efficient MRR using trimming technique;
- Explore, develop, and fabricate the PIC for the digital optical neural network (DONN) processor;
- Investigate and develop a multi-wavelength laser source with high wall-plug efficiency;
- Explore and develop the co-optimised EIC chip for high-resolution analog-to-digital conversion.
- Task 1.1: Design and development of power-efficient trimmable MRRs
Lead: SOTON - Task 1.2: PIC design for DONN
Lead: DTU - Task 1.3: Fabrication of PIC
Lead: SOTON - Task 1.4: Highly efficient integrated multi-wavelength light source
Lead: IMEC - Task 1.5: Co-optimized EIC for efficient ADC and data storage
Lead: TU/e
WP2: Development of digital optical computing platform
Objectives:
Develop
- DONN system packaging with PIC, EIC, laser, and FPGA with a chiplet design;
- Characterise the packaged DONN system;
- FPGA implementation for the generation of high-speed signals and PWM signals for the PIC, high-speed inputs for cache reading from EIC, and signal post-processing.
- Task 2.1: Chip packaging, high-speed PCB, and chiplet integration
Lead: TNO - Task 2.2: Characterization of co-packaged PIC, EIC, and multi-wavelength light source
Lead: DTU - Task 2.3: FPGA data interface
Lead: DTU
WP3: Performance evaluation in neural network
Objectives:
- Characterize fully packaged DONN system;
- Develop an NN compression algorithm;
- Performance evaluation and proof-of-concept demonstration of the DONN system with real-world tasks.
- Task 3.1: Matrix multiplication using digital optical computing platform
Lead: DTU - Task 3.2: NN compression and data preprocessing
Lead: KU - Task 3.3: Performance evaluation and real-world tests
Lead: KU
WP4: Communication, Dissemination and Exploitation
Lead: DTU
Objectives:
- Raise awareness of the project results;
- Identify and define exploitation activities and strategies;
- Secure funding for future developments;
- IPR protection and exploitation of the breakthrough technologies developed;
- Ensure data availability where appropriate.
- Task 4.1: Communication and dissemination plan
- Task 4.2: Post-project exploitation plan
- Task 4.3: Management and protection of IPR
- Task 4.4: Data management plan
- Task 4.5: Post-project sustainability plan
WP5: Project Management and Coordination
Lead: DTU
Objectives:
- To ensure an efficient administrative execution ;
- To assess the project progress and achieve timely submission of the project´s financial and scientific reports;
- To ensure compliance with the CA and EC requirements.
- Task 5.1: Project management and coordination
- Task 5.2: Risk management and contingency planning
- Task 5.3: Project meetings and Consortium communication
- Task 5.4: Periodic reporting
List of Project Deliverables
| No. | Deliverable Name | Leader | Type | Month |
|---|---|---|---|---|
| D1.1, D1.7 | Design and optimisation of the trimming fabrication processes for MRRs used in the PIC for DONN | SOTON | R | 18, 36 |
| D1.2 | Final PIC design and implementation for the DONN | DTU | R | 36 |
| D1.3, D1.4 | RP1, RP2: Multiwavelength laser, the design and implementation with predictability & reproducibility of wavelengths | IMEC | R | 36, 42 |
| D1.5, D1.6 | RP1, RP2: EIC chip, the architecture and implementation of Gbps-range mid-resolution ADCs in modern IC CMOS processes | TUE | R | 36, 42 |
| D2.1, D2.2 | RP, DEM: Packaged DONN system with chiplet integration | TNO | R, DEM | 33, 42 |
| D2.3 | DONN system characterization | DTU | R | 36 |
| D2.4 | FPGA implementation codes and setup for DONN | DTU | Other | 27 |
| D3.1 | NN compression algorithm | KU | R | 36 |
| D3.2, D3.3 | RP, DEM: Validated burst-mode DONN system | KU | R, DEM | 42, 48 |
| D3.4 | Matrix multiplication demo | DTU | DEM | 36 |
| D4.1 | Website and project logo | DTU | R | 3 |
| D4.2, D4.8 | RP1, RP2: Plan for Dissemination and Communication Activities | DTU | R | 6, 48 |
| D4.3, D4.9 | RP1, RP2: Plan for Exploitation Activities | DTU | R | 6, 48 |
| D4.4, D4.5, D4.6 | RP1, RP2, RP3: Data Management plan | DTU | DMP | 6, 30, 48 |
| D4.7 | IPR report with key exploitable results and protection | DTU | R | 48 |
| D4.10 | Post-project sustainability plan | DTU | R | 48 |
| D5.1 | RP1 Technical/scientific review meeting documents | DTU | R | 13 |
| D5.2 | RP2 Technical/scientific review meeting documents | DTU | R | 30 |
| D5.3 | RP3 Technical/scientific review meeting documents | DTU | R | 48 |